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19-3486; Rev 0; 11/04
10Gbps Clock and Data Recovery with Limiting Amplifier
General Description
The MAX3991 is a 10Gbps clock and data recovery (CDR) with limiting amplifier IC for XFP optical receivers. The MAX3991 and the MAX3992 (CDR with equalizer) form a signal conditioner chipset for use in XFP transceiver modules. The chipset is XFI compliant and offers multirate operation for data rates from 9.95Gbps to 11.1Gbps. The MAX3991 has 7mVP-P input sensitivity (BER 10-12), which allows direct connection to a transimpedance amplifier without the use of a stand-alone limiting amplifier. The phase-locked loop (PLL) is optimized for jitter tolerance and provides 0.6UI of high-frequency tolerance in SONET, Ethernet, and Fibre-Channel applications. The MAX3991 output provides 27% margin to the XFP eye mask specification. An AC-based power detector toggles the loss-of-signal (LOS) output when the input signal swing is below the user-programmed assert threshold. An external reference clock, with frequency equal to 1/64 or 1/16 of the serial data rate is used to aid in frequency acquisition. A loss-of-lock (LOL) indicator is provided to indicate the lock status of the receiver PLL. The MAX3991 is available in a 4mm x 4mm, 24-pin QFN package. It consumes 350mW from a single +3.3V supply and operates over the 0C to +85C temperature range.
Features
Multirate Operation from 9.95Gbps to 11.1Gbps 7mVP-P Input Sensitivity (BER 10-12) 0.6UIP-P Total High-Frequency Jitter Tolerance Low-Output Jitter Generation: 7mUIRMS Low-Output Deterministic Jitter: 4.6psP-P XFI-Compliant Output Interface LOS Indicator with Programmable Threshold LOL Indicator Power Dissipation: 350mW
MAX3991
Ordering Information
PART MAX3991UTG MAX3991UTG+* TEMP RANGE 0C to +85C 0C to +85C PINPACKAGE 24 QFN 24 QFN PKG CODE T2444-4 T2444-4
*Future product--contact factory for availability. +Denotes lead-free package.
Applications
REFCLKFCTL1
Pin Configuration
REFCLK+
9.95Gbps to 11.1Gbps Optical XFP Modules SONET OC-192/SDH STM-64 XFP Transceivers 10.3Gbps/11.1Gbps Ethernet XFP Transceivers 10.5Gbps Fibre-Channel XFP Transceivers 10Gbps DWDM Transceivers
TOP VIEW
VTH
LOS 20
24 VCC GND SDI+ SDIGND VCC 1 2 3 4 5 6 7 SCLKO+
23
22
21
LOL 19 18 VCC 17 GND 16 SDO+ 15 SDO14 GND 13 VCC 12 CFIL
MAX3991
Typical Application Circuit appears at end of data sheet.
8 SCLKO-
9 FCTL2
10 POL
11 VCC
4mm x 4mm QFN* *THE EXPOSED PAD MUST BE CONNECTED TO CIRCUIT-BOARD GROUND FOR PROPER THERMAL AND ELECTRICAL PERFORMANCE.
________________________________________________________________ Maxim Integrated Products
1
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC..............................................-0.5V to +4.0V Input Voltage Levels (SDI+, SDI-, REFCLK+, REFCLK-) ....................................(VCC - 1.0V) to (VCC + 0.5V) CML Output Voltage (SDO+, SDO-, SCLKO+, SLCKO-) ......................................(VCC - 1.0V) to (VCC + 0.5V) Voltage at (CFIL, LOL, VTH, POL, LOS, FCTL1, FCTL2) ..............................-0.5V to (VCC + 0.5V) Continuous Power Dissipation (TA = +85C) 24-Pin QFN (derate 20.8mW/C above +85C) .........1355mW Junction Temperature Range ............................-40C to +150C Storage Temperature Range...........................-55C to +150C Lead Temperature (soldering, 10s) ............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER Supply Current DATA INPUT SPECIFICATION (SDI) Single-Ended Input Resistance Differential Input Resistance Single-Ended Input Resistance Matching Differential Input Return Loss DC Cancellation Loop LowFrequency Cutoff REFERENCE CLOCK SPECIFICATION (REFCLK) Single-Ended Input Resisitance Differential Input Resistance CML OUTPUT SPECIFICATION (SDO) SDO Differential Output Swing SDO Output Common-Mode Voltage SCLKO Differential Output Single-Ended Output Resistance Differential Output Resistance Single-Ended Output Resistance Matching Differential Output Return Loss Common-Mode Output Return Rise/Fall Time Output AC Common Mode Power-Down Assert Time SDD22 SCC22 0.1GHz to 5.5GHz (Note 1) 5.5GHz to 12GHz (Note 1) 0.1GHz to 15GHz (Note 1) (20% to 80%) (Note 2) (Note 2) (Note 3) 18 13 8 5 23 30 10 50 RO 42 84 (Note 2) RL = 50 to VCC 575 650 VCC 0.16 380 50 100 58 116 5 725 mVP-P V mVP-P % dB dB ps mVRMS s 84 168 100 200 116 232 SDD11 0.1GHz to 5.5GHz (Note 1) 5.5GHz to 12GHz (Note 1) 12.5 6 30 RSE RD 42 84 50 100 58 116 5 % dB kHz SYMBOL ICC CONDITIONS MIN TYP 106 MAX 140 UNITS mA
2
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10Gbps Clock and Data Recovery with Limiting Amplifier
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER JITTER SPECIFICATION Jitter Peaking Jitter Transfer Bandwidth Sinusoidal Jitter Tolerance Jitter Generation Serial Data Output Deterministic Jitter DJ JP JBW 120kHz < f 8MHz (Notes 2, 4) f 120kHz (Notes 2, 4) (Notes 2, 4) f = 400kHz (Notes 2, 4, 6) (Notes 2, 4, 7) PRBS 27 - 1 (Note 2) f = 4MHz f = 80MHz 3.0 0.55 0.45 5.6 >3 (Note 5) >0.6 (Note 5) >0.5 (Note 5) 4.5 4.6 11.0 13 mUIRMS psP-P UIP-P 0.05 0.25 0.03 8.0 dB MHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3991
PLL ACQUISITION/LOCK SPECIFICATION Acquisition Time LOL Assert Time Maximum Frequency Pullin Time Frequency Difference at which LOL is Asserted Frequency Difference at which LOL is DeAsserted f/fREFCLK f/fREFCLK Figures 1, 2 (Note 2) Figure 1 (Note 2) (Note 8) f = |fVCO / N - fREFCLK|, N = 16 or 64 f = |fVCO / N - fREFCLK|, N = 16 or 64 2 651 500 200 90 s s ms ppm ppm
LOSS-OF-SIGNAL (LOS) SPECIFICATION VTH Control Voltage Range VTH VTH/ VLOS_ASSERT VLOS_ASSERT VLOS_ASSERT (Notes 2, 9) (Notes 2, 10) (Note 2) Overtemperature and supply Figure 2 (Note 2) Figure 2 (Note 2) -5 VIH VIL -30 VOH VOL Sourcing 30A Sinking 1mA VCC 0.5 0.4 2.0 0.8 +30 -1.5 3.5 -10 3 3.7 150 500 mV
LOS Gain Factor Minimum LOS Assert Voltage Maximum LOS Assert Voltage LOS Gain-Factor Accuracy LOS Hysteresis LOS Gain-Factor Stability LOS Assert Time LOS Deassert Time VTH Input Current
10 15 50 +1.5 3.9 +10 90 90 +5
V/V mV mV dB dB % s s A V V A V V
LVTTL INPUT/OUTPUT SPECIFICATION (LOL, LOS, FCTL1, FCTL2) Input High Voltage Input Low Voltage Input Current Output High Voltage Output Low Voltage
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
ELECTRICAL CHARACTERISTICS (continued)
(See Table 1 for operating conditions. Typical values at VCC = +3.3V, TA = +25C, unless otherwise noted.) Note 1: Measured with 100mVP-P differential amplitude. Note 2: Guaranteed by design and characterization. Note 3: Measured from the time that the FCTL1 input goes high with FCTL2 = 0 to the time when the supply current drops to less than 40% of the nominal value. Note 4: Measured with PRBS = 231 - 1. Note 5: Measurement limited by test equipment. Note 6: Jitter tolerance is for BER 10-12, measured with additional 0.1UI deterministic jitter and 40mVP-P differential input. Note 7: Measured with 50kHz to 80MHz SONET filter. Note 8: Applies on power-up, after standby. Note 9: Over process, temperature, and supply. Note 10: Hysteresis is defined as 20Log(VLOS-DEASSERT / VLOS-ASSERT).
Table 1. Operating Conditions (Unless otherwise noted, FCTL1 = FCTL2 = 0.)
PARAMETER Supply Voltage Ambient Temperature Input Data Rate SDI Differential Input Voltage Swing Load Resistance REFCLK Differential Input Voltage Swing REFCLK Duty Cycle REFCLK Frequency REFCLK Accuracy REFCLK Rise/Fall Times (20% to 80%) REFCLK Random Jitter fREFCLK Relative to Rb / 16 or Rb / 64 fREFCLK= Rb / 64 fREFCLK= Rb / 16 Noise bandwidth < 100MHz -100 SYMBOL VCC TA Rb VD RL RL is AC-coupled 300 30 Rb / 16 Rb / 64 +100 1200 300 10 15 50 1600 70 CONDITIONS MIN 3.0 0 (See Table 2 ) 1000 TYP MAX 3.6 +85 UNITS V C Gbps mVP-P mVP-P % GHz ppm ps psRMS
Table 2. Serial Data Rate and Reference Clock Frequency
APPLICATION OC-192 SONET - SDH64 OC-192 SONET Over FEC ITU G.709 10Gbps Ethernet, IEEE 802.3ae 10 Gigabit Ethernet Over ITU G.709 10Gbps Fibre Channel DATA RATE (Rb) (Gbps) 9.95328 10.664 10.709 10.3125 11.09573 10.51875 /16 REFERENCE CLOCK FREQUENCY (MHz) 622.08 666.5 669.3125 644.53125 693.483125 657.421875 /64 REFERENCE CLOCK FREQUENCY (MHz) 155.52 166.625 167.328125 161.1328125 173.3707813 164.355469
Note: The part should be in standby mode when data rates are being switched.
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
f/fREFCLK 651ppm 500ppm
LOL ASSERT TIME
ACQUISITION TIME
LOL *ASSERT AND ACQUISITION TIME ARE DEFINED WITH A VALID REFERENCE CLOCK APPLIED.
Figure 1. RX LOL Assert and PLL Acquisition Time
DATA INPUT POWER
LOS ASSERT TIME
LOS DEASSERT TIME
LOS
ACQUISITION TIME
LOL
Figure 2. LOS Assert/Deassert Time
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
Typical Operating Characteristics
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
MAX3991 OUPTUT AFTER XFP CONNECTOR (INPUT = 9.95328Gbps, 231-1 PATTERN, 10mVP-P)
MAX3991 toc01
MAX3991 OUTPUT (INPUT = 9.95328Gbps, 231-1 PATTERN)
MAX3991 toc02
JITTER GENERATION vs. POWER-SUPPLY WHITE NOISE AMPLITUDE (BW < 100kHz)
14 JITTER GENERATION (mUIRMS) 12 10 8 6 4 2 0
MAX3991 toc03
16
20ps/div
20ps/div
0
10
20
30
40
50
NOISE AMPLITUDE (mVRMS)
SUPPLY-INDUCED OUTPUT JITTER
ADDITIONAL OUTPUT JITTER (psP-P/mVP-P)
MAX3991 toc04
JITTER TOLERANCE vs. FREQUENCY
TOLERANCE EXCEEDS MODULATION CAPABILITIES OF TEST EQUIPMENT 10 SONET MASK
MAX3991 toc05
SINUSOIDAL JITTER TOLERANCE vs. INPUT AMPLITUDE
0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0 PATTERN = 231 -1 PRBS WITH 0.2UIP-P ADDITIONAL DETERMINISTIC JITTER, 10.095Gbps 0 10 20 30 40 50
MAX3991 toc06
0.07 0.06 0.05 0.04 0.03 0.02 0.01 0 1k 10k 100k FREQUENCY (Hz) 1M
100
0.45 80MHz JITTER TOLERANCE (U|P-P)
JITTER TOLERANCE (U|P-P)
1 INPUT = 30mVP-P, PRBS 231-1, 10.095Gbps, 0.2UIP-P 100k 1M FREQUENCY (Hz) 10M 100M
10M
0.1 10k
DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
BIT ERROR RATIO vs. INPUT AMPLITUDE
1.0E-00 1.0E-01 1.0E-02 1.0E-03 BIT ERROR RATIO 1.0E-04 1.0E-05 1.0E-06 1.0E-07 1.0E-08 1.0E-09 1.0E-10 1.0E-11 1.0E-12 4.5 5.0 5.5 6.0 6.5 7.0 DIFFERENTIAL INPUT AMPLITUDE (mVP-P)
MAX3991 toc07
JITTER TRANSFER
MAX3991 toc08
SUPPLY CURRENT vs. TEMPERATURE
MAX3991 toc09
3 0 JITTER TRANSFER (dB) -3
140 130 120 ICC (mA) 110 100 90 80
-6 -9 -12 -15 -18 -21 1k 10k 100k 1M 10M 100M FREQUENCY (MHz)
-5
10
25
40
55
70
85
AMBIENT TEMPERATURE (C)
6
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10Gbps Clock and Data Recovery with Limiting Amplifier
Typical Operating Characteristics (continued)
(VCC = 3.3V, TA = +25C, unless otherwise noted.)
MAX3991
SDD22 vs. FREQUENCY
MAX3991 toc10
SCC22 vs. FREQUENCY
MAX3991 toc11
LOS ASSERT/DEASSERT LEVELS vs. VTH VOLTAGE
DIFFERENTIAL INPUT AMPLITUDE (mVP-P) 140 120 100 80 60 ASSERT THRESHOLD 40 20 0 0 200 400 600 800 1000 1200 1400 1600 VTH VOLTAGE (mV)
MAX3991 toc12
10 5 0 -5 SDD22 (dB) -10 -15 -20 -25 -30 -35 -40 100M 1G 10G XFI
0 -5 XFI -10 SCC22 (dB) -15 20 -25 -30 -35 100M
160 DEASSERT THRESHOLD
100G
1G
10G
100G
FREQUENCY (mHz)
FREQUENCY (Hz)
Pin Description
PIN 1, 6, 11, 13, 18 2, 5, 14, 17 3 4 7 8 9 10 12 15 16 19 20 NAME VCC GND SDI+ SDISCLKO+ SCLKOFCTL2 POL CFIL SDOSDO+ LOL LOS +3.3V Power Supply Supply Ground Positive Serial Input, CML Negative Serial Input, CML Positive Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). Negative Clock Output, CML. See Table 3 for information about enabling the SCLKO output (for use in device testing). Function Control Input 2, TTL. See Table 3 for more information. Data Polarity Control Input, TTL. Connect to VCC or leave open to maintain the same polarity as the input. Connect to GND to invert the polarity of the data. Loop-Filter Capacitor Connection. Connect a 0.047F capacitor between CFIL and VCC. Negative Serial Data Output, CML Positive Serial Data Output, CML Lock Status Indicator, TTL. This output goes high to indicate the receiver is out of lock. Receiver Loss-of-Signal Indicator, TTL . This output goes high when the input signal drops below the programmed threshold. FUNCTION
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
Pin Description (continued)
PIN NAME FUNCTION Positive Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK have a 200 differential impedance. See the Detailed Description section for more information. See Table 2. Negative Reference Clock Input, Digital. The REFCLK inputs are designed to be AC-coupled to the reference clock source. REFCLK have a 200 differential impedance. See the Detailed Description section for more information. See Table 2. Function Control Input 1, TTL. See Table 3 for more information. LOS Threshold Input, Analog. A voltage applied to this input sets the LOS assert threshold. The LOS power detector can be disabled if VTH is connected to VCC, which forces LOS low. Supply Ground. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical performance. The MAX3991 uses exposed-pad variation T2444-4 in the package outline drawing. See the exposed-pad package.
21
REFCLK+
22
REFCLK-
23 24
FCTL1 VTH Exposed Pad
EP
Functional Diagram
VTH LOS
MAX3991
SDI+ SDICML LIMITING AMPLIFIER PLL PHASE/ FREQUENCY DETECTOR D
DFF Q CML SDO+ SDO-
VCO
CML
SCLKO+ SCLKO-
REFCLK+ REFCLK-
200
LOL DETECTOR
FUNCTIONAL CONTROL FCTL1 FCTL2 POL
LOL
CFIL
Figure 3. Functional Diagram
Detailed Description
The MAX3991 clock and data recovery with limiting amplifier restores data to XFI specifications. It consists of a limiting amplifier with LOS power detector, and a PLL data retimer with LOL indicator. An optional recovered clock may also be enabled for performance testing.
Limiting Amplifier
The SDI inputs of the MAX3991 accept serial NRZ data from the optical receiver assembly. The limiting amplifier accepts signals as small as 7mVP-P and amplifies them to allow recovery by the CDR. The limiting amplifier uses an offset cancellation circuit to compensate for device mismatch within the gain stages. The low-frequency cutoff of the offset cancellation loop is typically 30kHz.
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10Gbps Clock and Data Recovery with Limiting Amplifier
PLL Retimer
The integrated PLL recovers a synchronous clock, which is used to retime the input data. Connect a 0.047F capacitor between CFIL and VCC to provide PLL dampening. The external reference connected to REFCLK aids in frequency acquisition. Because the reference clock is only used for frequency acquisition, a low-quality reference clock can be used with no penalty in performance. The reference clock should be within 100ppm of the bit rate divided by 16 or 64.
Reference Clock Input
The REFCLK inputs are internally terminated and selfbiased to allow AC-coupling. The input impedance is 100 single-ended (200 differential). The REFCLK inputs of the MAX3991 and MAX3992 should be connected close together in parallel. The impedance looking into the parallel combination is 100 differential. This allows both the MAX3991 and MAX3992 to easily interface with one reference clock without using additional components. See Figure 5.
MAX3991
Loss-of-Lock Monitor
The LOL output indicates that the frequency difference between the recovered clock and the reference clock is excessive. LOL may assert due to excessive jitter at the data input, incorrect frequency, or loss of input data. The LOL detector monitors the frequency difference between the recovered clock and the reference clock. The LOL output is asserted high when the frequency difference exceeds 650ppm.
Design Procedure
Modes of Operation
The MAX3991 has a standby mode, jitter test mode, and squelch mode in addition to its normal operating mode. Standby is used to conserve power. In the standby mode, the power consumption of the MAX3991 falls below 40% of the normal-operation power consumption. The jitter test mode enables the SCLK outputs to clock a BERT when testing jitter generation, jitter transfer, and jitter tolerance. In the squelch mode, the SDO outputs are held static at VCC. The FCTL1 and FCTL2 TTL inputs are used to select the mode of operation as shown in Table 3.
Loss-of-Signal Monitor
The LOS output indicates low, receive-signal power. The LOS output is asserted high when the input signal is below the threshold set by VTH. VTH = 10 x VLOS_ASSERT(mVP-P) (typ) The hysteresis value of the LOS detector is internally fixed at 1.5. Hysteresis values above 1.5 can be achieved using external resistors as shown in Figure 4. The new hysteresis value is: Hysteresis = 1.5 x 3 x R1 + VREF x R2 0.2 x R1 + VREF x R2
Serial Data Rate and Reference Clock Frequency
Input Configuration The SDI inputs of the MAX3991 are current-mode logic (CML) compatible. The inputs have internal 50 terminations for minimum external components. See Figure 6 for the input structure. AC-coupling is recommended. The common-mode levels of DC-coupled parts must be matched. For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
Resistor R2 is selected to prevent loading of the LOS pin. A value of >40k is recommended. Refer to applications note HFDN 34-0.
Output Configuration
The MAX3991 uses CML for its high-speed digital outputs (SDO and SCLKO). The configuration of the output circuit includes internal 50 back terminations to VCC. See Figure 7 for the output structure. CML outputs may be terminated by 50 to VCC, or by 100 differential impedance. The relation of the output polarity to input can be reversed using the POL pin (see Figure 8). For additional information on logic interfacing, refer to Maxim Application Note HFAN 1.0: Introduction to LVDS, PECL, and CML.
LOS R2 R1 VTH VREF
MAX3992
Figure 4. Added Hysteresis Circuit
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
MAX3991
200 50 REFERENCE CLOCK 50
50 REFERENCE CLOCK
50 200
MAX3991
200
RECEIVER-ONLY TERMINATION
MAX3992
200
TRANSCEIVER TERMINATION
Figure 5. Reference Clock Termination
Table 3. Functional Control
FCTL1 0 1 0 1 FCTL2 0 0 1 1 DESCRIPTION Normal operation, serial clock output disabled. Standby power-down mode. Serial data output disabled. Serial clock output enabled for jitter testing.
SDISDI+ 50
VCC
50
Applications Information
Exposed Pad (EP) Package
The exposed pad, 24-pin QFN incorporates features that provide a very low thermal-resistance path for heat removal from the IC. The pad is electrical ground on the MAX3991 and must be soldered to the circuit board for proper thermal and electrical performance.
Figure 6. CML Input Model
Layout Considerations
For best performance, use good high-frequency layout techniques. Filter voltage supplies, keep ground connections short, and use multiple vias where possible. Use controlled-impedance transmission lines to interface with the MAX3991 high-speed inputs and outputs. Power-supply decoupling should be placed as close to VCC as possible. To reduce feedthrough, take care to isolate the input signals from the output signals.
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
VCC
50
50 SDO+
SDO-
GND
Figure 7. CML Output Model
(SDI+) - (SDI-)
(SDO+) - (SDO-) POL = VCC
(SDO+) - (SDO-) POL = GND
Figure 8. Polarity (POL) Function
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10Gbps Clock and Data Recovery with Limiting Amplifier MAX3991
Typical Application Circuit
VCC 0.047F TOSA
CFIL
SDO+
VCC
GND
SDI+
MAX3975
DRIVER SDO-
SDI-
MAX3992
FCTL VTH POL
2 N.C.
REFCLK+ REFCLK-
LOL LOS
DS1862* CONTROLLER
2
30-PIN CONNECTOR
2-WIRE INTERFACE
N.C.
LOL LOS
SDI+ RO5A SDI-
FCTL VTH POL
REFCLK+ REFCLK-
MAX3991
CFIL VCC GND
SDO+ SDO-
0.047F 50 TRANSMISSION LINE *FUTURE PRODUCT
XFI REFERENCE
VCC
Chip Information
TRANSISTOR COUNT: 10,300 PROCESS: SiGe bipolar SUBSTRATE: SOI
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maximic.com/packages.) (QFN 4mm x 4mm x 0.8mm, package code: T2444-4)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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